• ASA-EMulatR Reference Guide
  • License 
  • Acknowledgements
  • Introduction
    • Architecture Overview
      • Chapter 1 - System Overview
        • 1.1 Purpose and Audience
        • 1.2 Design Goals and Guiding Principles
        • 1.3 Target Architecture
        • 1.4 Major Architectural Layers
        • 1.5 Non-Goals
        • 1.6 Control and Data Flow
        • 1.7 Architectural Invariants
        • 1.8 How to Read This Guide
      • Chapter 2 - Execution Model
        • 2.1 Purpose of this Chapter
        • 2.2 Cycle-Base Execution Model
        • 2.3 Responsibilities of the AlphaCPU Run Loop
        • 2.4 Execution Phases per Cycle
        • 2.5 Execution Progress and Stalls
        • 2.6 Speculation Policy
        • 2.7 Execution and Commit Semantics
        • 2.8 Interaction with SMP Systems
        • 2.9 Relationship to Other Chapters
        • 2.10 Summary
      • Chapter 3 - Pipeline Architecture
        • 3.1 Pupose of this Chapter
        • 3.2 Overview of the Pipeline Model
        • 3.3 The Six Pipeline Stages
        • 3.4 Fetch Stage (IF)
        • 3.5 Decode Stage (ID)
        • 3.6 Issue Stage (IS)
        • 3.7 Execute Stage (EX)
        • 3.8 Memory Stage (MEM)
        • 3.9 Writeback Stage (WB)
        • 3.10 PipelineSlot Contract
        • 3.11 Backward Pipeline Advancement
        • 3.12 Stalls and Serialization 
        • 3.13 Flushing and Speculation
        • 3.14 Precise Exceptions 
        • 3.15 LL/SC Interaction with the Pipeline
        • 3.16 Grain System 
        • 3.17 Relationship to Other Chapters
        • 3.18 Summary
      • Chapter 4 - Functional Execution Domains ("Boxes)
        • 4.1 Purpose of This Chapter
        • 4.2 Box-Based Execution Model
        • 4.3 Execution Flow: Grains, Pipeline, and Boxes
        • 4.4 IBox - Instruction Box
        • 4.5 EBox - Execution Box (Integer Core)
        • 4.6 FBox - Floating-Point Box
        • 4.7 MBox - Memory Box
        • 4.8 CBox - Cache / Coherency / Coordination Box
        • 4.9 PalBox - Privileged Architecture Library Box
        • 4.10 Cross-Box Interaction Rules
        • 4.11 Summary
      • Chapter 5 - Memory System Architecture
        • 5.1 Purpose of This Chapter
        • 5.2 Design Philosophy
        • 5.3 Memory Layers Overview
        • 5.4 Virtual Addressing and Translation
        • 5.4.4 Alpha VA Field Boundary Reference
        • 5.5 GuestMemory - Shared Physical Memory
        • 5.6 SafeMemory - Phsyical RAM Backend
        • 5.7 MMIO Regions
        • 5.8 Loads and Stores
        • 5.9 Write Buffers
        • 5.10 Memory Barriers (preview)
        • 5.11 Load-Locked / Store-Conditional (LL/SC)
        • 5.12 Memory Faults
        • 5.13 Interaction with Pipeline
        • 5.14 SMP Considerations
        • 5.15 Summary
      • Chapter 6 - Serialization and Stall Model
        • 6.1 Purpose of This Chapter
        • 6.2 Weak Ordering as the Default
        • 6.3 What Serialization Means
        • 6.4 Classes of Serialization Instructions
        • 6.5 Pipeline-Level Behavior
        • 6.6 Barrier Release Model
        • 6.7 MB - Full Memory Barrier
        • 6.8 WMB - Write Memory Barrier
        • 6.9 EXCB - Exception Barrier
        • 6.10 TRAPB - Trap Barrier
        • 6.11 CALL_PAL as a Serialization Point
        • 6.12 Interaction with LL/SC
        • 6.13 Serialization in SMP Systems 
        • 6.14 Summary
      • Chapter 7 - Exceptions, Faults, and Interrupts
        • 7.1 Purpose of This Chapter
        • 7.2 Terminology and Classification
        • 7.3 ExceptionClass Classification
        • 7.4 Exception Detection Points
        • 7.5 FaultDispatcher
        • 7.6 PendingEvent Structure
        • 7.7 Priority Ordering
        • 7.8 Precise Exception Model
        • 7.9 Exception Delivery and PAL Mode Entry
        • 7.10 Interrupt Handling
        • 7.11 Traps and TRAPB
        • 7.12 Interaction with Serialization and LL/SC
        • 7.13 Summary
      • Chapter 8 - PAL and Privileged Boundary
        • 8.1 Purpose of This Chapter
        • 8.2 What PAL is (and is Not)
        • 8.3 Privilege Levels
        • 8.4 CALL_PAL - Entering the Privileged Boundary
        • 8.5 PAL Vector Dispatch
        • 8.6 PAL Execution Model
        • 8.7 PAL and Exceptions/Interrupts
        • 8.8 PAL and Memory Ordering
        • 8.9 HW_REI - Exiting PAL Mode
        • 8.10 Enforcing the Privileged Boundary
        • 8.11 PAL and LL/SC Reservations
        • 8.12 PAL Register Matrix
        • 8.13 Summary
      • Chapter 9 - SMP Architecture
        • 9.1 Purpose of This Chapter
        • 9.2 SMP Design Philosophy
        • 9.3 CPU Instantiation and Identity
        • 9.4 Per-CPU vs Shared State
        • 9.5 Memory Visibility in SMP
        • 9.6 Inter-Processor Interrupts (IPIs)
        • 9.7 Memory Barrier Coordination
        • 9.8 TLB Shootdown
        • 9.9 Reservation Invalidation in SMP
        • 9.10 PAL and SMP
        • 9.11 Exception and Interrupt Isolation
        • 9.12 Debugging SMP Behavior
        • 9.13 Summary
      • Chapter 10 – Devices and Memory-Mapped I/O (MMIO)
        • 10.1 Purpose of This Chapter
        • 10.2 Design Philosophy
        • 10.3 Device Model Overview
        • 10.4 Device Registration and Catalog
        • 10.5 MMIOManager - MMIO Address Space
        • 10.6 MMIO Access Semantics
        • 10.7 Device Registers and Side Effects
        • 10.8 Asynchronous Operations and DMA
        • 10.9 Interrupt Signaling
        • 10.10 MMIO and Serialization
        • 10.11 PAL and Device Control
        • 10.12 SMP and Error Handling
        • 10.13 Summary
      • Chapter 11 - Architectural Invariants
        • 11.1 Purpose of This Chapter
        • 11.2 Execution and Pipeline Invariants
        • 11.3 Memory Model Invariants
        • 11.4 Load-Locked / Store-Conditional Invariants
        • 11.5 Privilege and PAL Invariants
        • 11.6 Exception and Interrupt Invariants
        • 11.7 SMP Invariants
        • 11.8 Device and MMIO Invariants
        • 11.9 Debugging and Observability Invariants
        • 11.10 Invariant Violations
        • 11.11 Summary
      • Chapter 12 – AlphaCPU Core
        • 12.1 Purpose of This Chapter
        • 12.2 AlphaCPU as the Unit of Execution
        • 12.3 Ownership Model
        • 12.4 CPU Lifecycle
        • 12.5 The AlphaCPU Run Loop
        • 12.6 Pipeline Integration
        • 12.7 Interrupt and Exception Handling
        • 12.8 PAL Integration
        • 12.9 SMP Awareness
        • 12.10 CPU-Local Events
        • 12.11 Error Handling
        • 12.12 Performance and Instrumentation
        • 12.13 Summary
      • Chapter 13 – AlphaPipeline Implementation
        • 13.1 Purpose of This Chapter
        • 13.2 Pipeline Role and Design
        • 13.3 Pipeline Structure - Ring Buffer
        • 13.4 PipelineSlot Structure
        • 13.5 Pipeline Execution - tick() and execute()
        • 13.6 Stage Implementations
        • 13.7 Stall Mechanics
        • 13.8 Flush Semantics
        • 13.9 Serialization and Barriers in Pipeline
        • 13.10 Exception Precision
        • 13.11 Branch Handling
        • 13.12 LL/SC and Determinism
        • 13.13 Summary
      • Chapter 14 – Execution Domains (“Boxes”)
        • 14.1 IBox – Instruction Box
        • 14.2 EBox – Integer Execution Box
        • 14.3 FBox – Floating-Point Execution Box
        • 14.4 MBox – Memory Box
        • 14.5 CBox – Cache / Control Box
        • 14.6 PalBox – Privileged Architecture Library Execution Box
        • 14.7 Box Interaction Model
        • 14.8 Repository Directory Mapping
      • Chapter 15 – Memory System Implementation Details
        • 15.1 Memory Is Shared, Not Owned
        • 15.2 GuestMemory vs SafeMemory (Critical Separation)
        • 15.3 GuestMemory Region Support and PA Routing
        • 15.4 SparseMemoryBacking – On-Demand Page Allocator
        • 15.5 Load and Store Semantics
        • 15.6 Write Buffer Implementation
        • 15.7 MMIO Access Semantics
        • 15.8 LL/SC Reservation Tracking
        • 15.9 Memory Barrier Coordination
        • 15.10 SMP Visibility Guarantees
        • 15.11 Memory Fault Handling
        • 15.12 Diagnostics and DMA Coherency
        • 15.13 Architectural Invariants (Normative)
        • 15.14 Repository Directory Mapping
      • Chapter 16 – Device Model & DMA
        • 16.1 Device Differentiation and Class Hierarchy
        • 16.2 MMIO Routing Implementation
        • 16.3 Endianness and Device Registers
        • 16.4 Asynchronous Device Threading (QThread Model)
        • 16.5 SCSI Subsystem
        • 16.6 Tape Drive Emulation and Format Variants
        • 16.7 Network and Fibre Channel Devices
        • 16.8 IRQ Integration Architecture
        • 16.9 DMA Implementation
        • 16.10 Device Registration and Template System
        • 16.11 Architectural Invariants (Normative)
        • 16.12 Repository Directory Mapping
      • Chapter 17 – Address Translation, TLB, and PTE
        • 17.1 Alpha Virtual Address Format
        • 17.2 PTE Representation
        • 17.3 Translation Path
        • 17.4 SPAM TLB Cache Architecture
        • 17.5 Ev6SiliconTLB and Layer Architecture
        • 17.6 Replacement Policies
        • 17.7 ASN Management and Coherence
        • 17.8 TLB Invalidation and Shootdown
        • 17.9 IBox Instruction Translation
        • 17.10 Architectural Invariants (Normative)
        • 17.11 Repository Directory Mapping
      • Chapter 18 – Fault Dispatcher & Precise Exceptions
        • 18.1 Exception Classification
        • 18.2 PendingEvent Structure
        • 18.3 ExceptionFactory
        • 18.4 FaultDispatcher Implementation
        • 18.5 Exception-to-PAL Vector Mapping
        • 18.6 Pipeline Fault Detection and Delivery Flow
        • 18.7 PAL Mode Entry
        • 18.8 Precise Exception Guarantees
        • 18.9 Barrier Interaction
        • 18.10 Architectural Invariants (Normative)
        • 18.11 Repository Directory Mapping
      • Chapter 19 – Interrupt Architecture & IPI
        • 19.1 Interrupt Sources
        • 19.2 IRQPendingState Implementation
        • 19.3 Interrupt Routing
        • 19.4 Interrupt Sampling and Delivery
        • 19.5 IPI Architecture
        • 19.6 Memory Barrier Coordination
        • 19.7 TLB Shootdown Protocol
        • 19.8 Architectural Invariants (Normative)
        • 19.9 Repository Directory Mapping
      • Chapter 20 – Boot Sequence, PAL, and SRM Integration
        • 20.1 PalBox Execution Domain
        • 20.2 PalService Delegation
        • 20.3 CALL_PAL Dispatch and Vector Calculation
        • 20.4 PAL Mode Entry and Exit
        • 20.5 Shadow Registers and HWPCB
        • 20.6 Privileged Instructions
        • 20.7 PAL Function Inventory
        • 20.8 CSERVE and SRM Console Integration
        • 20.9 Boot Sequence
        • 20.10 Architectural Invariants (Normative)
        • 20.11 Repository Directory Mapping
      • Chapter 21 – Debugging, Tracing, and Determinism
        • 21.1 Determinism as a Design Goal
        • 21.2 Sources of Nondeterminism
        • 21.3 EXECTRACE Instrumentation System
        • 21.4 Subsystem Logging (DEBUG_LOG)
        • 21.5 Tracing by Subsystem
        • 21.6 LogReader Diagnostic Application
        • 21.7 Breakpoints and Watchpoints
        • 21.8 Deterministic Replay
        • 21.9 SMP Debugging Considerations
        • 21.10 Architectural Invariants (Normative)
        • 21.11 Repository Directory Mapping
      • Chapter 22 – Testing, Validation, and Architectural Compliance
        • 22.1 Definition of Correctness
        • 22.2 Layered Validation Strategy
        • 22.3 Determinism as a Validation Tool
        • 22.4 Exception and Fault Validation
        • 22.5 Memory Ordering and LL/SC Validation
        • 22.6 PAL and Privilege Boundary Validation
        • 22.7 Device and DMA Validation
        • 22.8 Regression Testing Policy
        • 22.9 Architectural Compliance Matrix
        • 22.10 Known Deviations and Non-Goals
        • 22.11 Architectural Invariants (Normative)
        • 22.12 Final Compliance Statement
    • Appendix
      • Appendix A - Topics - Core
        • A.1 – Core Types Reference
        • A.2 – EV6 Internal Processor Register (IPR) Reference
        • A.3 – Global Singletons
        • A.4 – Endianness Rules
      • Appendix B - Branch Prediction Mechanics
      • Appendix C – Physical Address Memory Map
      • Appendix D – Repository Directory Structure
      • Appendix F - SPAM (PTE/Translation Buffer)
      • Appendix G - Instruction Grain Mechanics
        • G.1 – DecodedInstruction Quick Reference
        • G.2 – Instruction Inventory (GrainMaster.tsv)
        • G.3 - GrainMaster.tsv
      • Appendix H - Alpha Pipeline 
        • H.1 - Pipeline Cycle Mechanics
        • H.2 - Pipeline Retirement Mechanics
      • Appendix I – Glossary and Acronyms
      • Appendix J - SRM Firmware Topic Hive
        • J.1 - ROM Loader: Descriptor Derivation and Snapshot Validation
        • J.2 - SRM-D Configuration and Initialization
        • J.3 - SRM-D Snapshot Mechanics
        • J.4 - SRM Firmware Initialization and PAL Exception Dispatch
        • J.5 - SRM-D Full Cycle Execution
      • Appendix K - CpuTrace