<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 1 - System Overview > 1.7 Architectural Invariants

The following rules must always hold. Violating any invariant is a correctness bug, not an optimization opportunity. These invariants are authoritative — Chapter 11 provides the complete normative enumeration.

 

•Writeback (WB) is the sole architectural commit point — no earlier stage produces visible state changes

•All exceptions are precise and ordered — when delivered, all prior instructions have completed and no later instruction has modified architectural state

•No speculative execution past serialization points (MB, WMB, EXCB, TRAPB, CALL_PAL, HW_REI)

•GuestMemory is the sole authority for physical memory visibility and SMP coherency

•Memory is weakly ordered by default — ordering is enforced only by explicit barriers or PAL operations

•MMIO accesses are strongly ordered, synchronous, and never buffered

•One LL/SC reservation per CPU — reservations are cleared on exception delivery

•PAL execution serializes the pipeline — CALL_PAL is a serialization boundary

•Each CPU has an independent pipeline, register files, and TLBs — no CPU may observe another CPU's internal execution state

•One run-loop iteration equals one hardware clock cycle

•All instruction semantics execute in the EX stage — other stages perform bookkeeping only

•Dependency flow is strictly one-way: ExecutionCoordinator → AlphaCPU → IBox → Pipeline/Boxes → GuestMemory/FaultDispatcher

 

See Also: Chapter 11 - Architectural Invariants (complete normative list).