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ASN — Address Space Number. 8-bit identifier distinguishing TLB entries by process; avoids TLB flush on context switch when ASN changes.

COW — Copy-On-Write. Deferred page duplication on write fault; supported in the PTE subsystem via fault-on-write permission bits.

CM — Current Mode. Processor privilege level (0=Kernel, 1=Executive, 2=Supervisor, 3=User), stored in the PS register.

DTB — Data Translation Buffer. TLB for data accesses. EV6 uses a dual DTB0/DTB1 architecture.

EXCB — Exception Barrier. Ensures all prior instructions complete and all pending exceptions are resolved before any younger instruction issues.

FPCR — Floating Point Control Register. Controls rounding mode, trap enables, and records exception status for IEEE 754 compliance.

Grain — The emulator's atomic execution unit. Each instruction maps to one grain via the InstructionGrainRegistry; grains implement the execute() method that performs the instruction's architectural effect.

HWPCB — Hardware Privileged Context Block. Per-CPU/per-process context structure holding PC, PS, stack pointers, AST state, and IPR values. Saved/restored by PAL during context switches and exception handling.

HWRPB — Hardware Restart Parameter Block. System configuration data structure populated during boot, describing processor type, memory size, cache parameters.

IPI — Inter-Processor Interrupt. CPU-to-CPU notification used for TLB shootdowns, barrier synchronization, and SMP coordination.

IPL — Interrupt Priority Level. 4-bit field (0–7) in the PS register; interrupts at or below the current IPL are masked.

IPR — Internal Processor Register. Hardware-internal registers accessible only through HW_MFPR/HW_MTPR in PAL mode.

ITB — Instruction Translation Buffer. TLB for instruction fetches.

LL/SC — Load-Locked / Store-Conditional. Atomic memory primitive pair (LDx_L / STx_C) for lock-free synchronization.

MB — Memory Barrier. Full memory ordering fence; in SMP requires global coordination via MemoryBarrierCoordinator.

MMIO — Memory-Mapped I/O. Device register access via physical address ranges routed through MMIOManager.

PAL — Privileged Architecture Library. Hardware-defined privileged execution environment providing exception dispatch, interrupt handling, IPR access, and context switching.

PDE — Page Directory Entry. Upper-level page table entry pointing to next-level page table (Alpha uses three-level page tables).

PFN — Page Frame Number. Physical page identifier extracted from a PTE.

PS — Processor Status. Architectural register containing CM, IPL, and condition code state.

PTE — Page Table Entry. Translation table entry mapping virtual page to physical frame with permission and status bits.

PTW — Page Table Walker. Hardware/software mechanism that walks the three-level page table on TLB miss.

SCB — System Control Block. Table of exception and interrupt vectors pointed to by SCBB IPR.

SPAM — Set Prediction and Access Memory. The emulator's software TLB cache layer implementing per-CPU sharded PTE caching with configurable replacement policies.

SRM — System Reference Manual console firmware. The pre-boot console providing the >>> prompt, environment variables, and boot services.

TLB — Translation Lookaside Buffer. Hardware cache of virtual-to-physical address translations. A TLB hit avoids a page table walk; a TLB miss triggers a refill from the page table.

TRAPB — Trap Barrier. Ensures all prior instructions that may generate traps have completed before proceeding.

WMB — Write Memory Barrier. Local write ordering fence; drains the local write buffer but does not require global SMP coordination.

 

See Also: Alpha Architecture Reference Manual – Glossary; Chapter 2 - Execution Model.