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2.1 Cycle-Based Execution

 

EMulatR operates on a cycle-based execution model where each iteration of the AlphaCPU run loop represents one hardware clock cycle.

 

Each CPU executes independently but synchronizes with shared subsystems as required.

 

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2.2 Run Loop Responsibilities

 

This section describes the responsibilities of the AlphaCPU run loop at a conceptual level:

 

•Pipeline advancement

•Exception and interrupt delivery

•Barrier enforcement

•SMP coordination

•State updates

 

Implementation details are covered in the AlphaCPU chapter.

 

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2.3 Forward Progress and Stalls

 

This section defines the conditions under which forward progress may be temporarily suspended, and the mechanisms by which execution resumes.