<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 2 - Execution Model > 2.1 Purpose of This Chapter

This chapter defines the execution model of EMulatR. It explains how AlphaCPU instances advance instructions, how cycles are defined and processed, how stalls and serialization are enforced, and how execution interacts with SMP systems.

 

Specifically, this chapter:

•Defines the architectural execution contract — one run-loop iteration equals one hardware clock cycle

•Establishes deterministic cycle-based behavior as the foundation of all execution

•Describes stall sources and serialization handling

•Defines exception and interrupt delivery rules

•Specifies the execute-stage authority and writeback commit contract

 

This chapter is normative. All execution-related subsystems must conform to the rules defined here. This chapter defines when and why execution progresses or pauses; it does not define how individual instructions behave (see Chapter 4 — Execution Domains), how memory ordering is enforced (see Chapter 6 — Serialization), or how PAL handlers work (see Chapter 8 — PAL).

 

See Also: Chapter 3 - Pipeline Architecture; Chapter 12 – AlphaCPU Core (implementation).