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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 12 – AlphaCPU Core |
The AlphaCPU Core represents the central execution engine of EMulatR. It is responsible for maintaining architectural state, coordinating instruction execution, managing traps and interrupts, and enforcing the behavioral guarantees defined by the Alpha AXP System Architecture.
This component does not model physical silicon or pipeline timing at the microarchitectural level. Instead, it implements the architectural contract of the Alpha processor — ensuring that all visible state transitions, exceptions, memory ordering semantics, and privilege boundaries conform to the specification.
The AlphaCPU Core serves as the authoritative owner of:
•Program Counter (PC) state
•Integer and floating-point register files
•Processor Status and mode control
•Trap and exception dispatch
•Interrupt level management (IPL)
•Memory ordering and barrier semantics
•Per-CPU execution lifecycle
The AlphaCPU Core performs the following major functions:
•Instruction Lifecycle Management
•The CPU core controls the per-cycle execution loop, including:
•Instruction fetch coordination
•Decode dispatch routing
•Execution domain selection (Integer, FP, Vector, Control)
•Writeback and architectural state update
•Precise exception tracking
Each instruction must either complete fully or generate a precise trap as defined by the Alpha architecture.
The AlphaCPU Core is the single authoritative owner of architectural state for a processor instance. This includes:
•32 integer registers
•32 floating-point registers
•Program counter and next-PC sequencing
•Processor mode and privilege transitions
•Interrupt Priority Level (IPL)
•Trap state
State transitions occur only through well-defined execution paths to preserve determinism and correctness.
The Alpha architecture requires precise exception behavior. The AlphaCPU Core ensures that:
•Exceptions are reported in architectural order
•Faulting instructions do not partially commit state
•Barrier instructions enforce ordering guarantees
•Trap vectors are dispatched correctly
•PAL entry and return sequences preserve architectural integrity
•Trap handling is deterministic and SMP-safe.
Alpha’s weak memory ordering model requires explicit enforcement of barrier semantics. The CPU Core ensures that:
•MB, WMB, and related instructions serialize operations appropriately
•Memory operations obey architectural visibility rules
•SMP interactions remain race-free and deterministic
The CPU does not speculate beyond architectural guarantees.
Each AlphaCPU instance represents a single logical processor. In multiprocessor configurations:
•Each CPU maintains independent architectural state
•Inter-processor interrupts (IPI) are delivered via the interrupt subsystem
•Memory visibility and barrier semantics are preserved
•Trap and interrupt resolution remains per-CPU
•The AlphaCPU Core is therefore both isolated and coordinated.
The AlphaCPU Core is designed according to the following principles:
Architectural correctness over microarchitectural mimicry
•Explicit control over state transitions
•Clear separation of concerns
•Deterministic execution behavior
•Strict privilege boundary enforcement
It intentionally avoids modeling speculative execution or cache timing characteristics that are not architecturally visible.
Within the EMulatR layered architecture, the AlphaCPU Core sits between:
•The execution domain layers (IntegerExecutor, FloatingPointExecutor, VectorExecutor, ControlExecutor)
•The memory subsystem
•The interrupt controller
•The PAL interface layer
It orchestrates these subsystems while remaining the single point of truth for processor state.
This chapter describes:
•The structure and responsibilities of the AlphaCPU class
•Execution loop design
•Trap dispatch mechanics
•Interaction with the executor hierarchy
•Memory ordering integration
•SMP coordination mechanisms
The AlphaCPU Core forms the architectural nucleus of EMulatR and provides the foundation upon which firmware bring-up and operating system execution are built.