ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 11

Architectural invariants define what EMulatR is. They are the foundation on which all future features must stand.

1.Precise execution — all exceptions precise, single commit point in WB, detect-early/deliver-late model

2.EX stage authority — all instruction semantics execute in EX, no architectural work in other stages

3.Explicit ordering — weak ordering by default, ordering only via barriers/PAL/MMIO, no implicit guarantees

4.Absolute privilege separation — PAL or non-PAL (binary), CALL_PAL only entry, HW_REI only exit, full state save/restore

5.Correct atomic semantics — reservations per-CPU, cache-line granular, cleared on every privilege boundary

6.Strong MMIO correctness — synchronous, strongly ordered, never buffered, never speculative

7.PAL-mediated control — all exceptions and interrupts enter PAL, no bypass

8.Deterministic SMP — true symmetry, per-CPU independence, explicit coordination only

9.Full observability — every architectural event traceable, CPUId in all logs

10.No invariant may be violated — correctness overrides performance, convenience, and simplicity

11.11 Summary