<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 11 - Architectural Invariants > 11.10 Invariant Violations

Any violation of an architectural invariant indicates a design bug or an implementation defect. Performance, convenience, or simplicity never justify violating an invariant.

 

Common violation patterns to watch for:

•Architectural state modified before WB stage — violates single commit point (11.2.2)

•Implicit ordering assumed between CPUs — violates weak ordering (11.3.1)

•LL/SC reservation survives PAL transition — violates reservation lifetime (11.4.2)

•Speculative instruction executes past barrier — violates serialization (11.2.4)

•Exception delivered with younger instructions committed — violates precise execution (11.2.1)

•MMIO access buffered or reordered — violates MMIO strong ordering (11.3.3)

•Exception bypasses PAL entry — violates PAL-mediated delivery (11.6.3)

•One CPU directly mutates another's pipeline state — violates per-CPU independence (11.7.2)

 

Machine checks (MachineCheckReason::SMP_BARRIER_TIMEOUT) are the system's last defense against invariant violations that would otherwise deadlock SMP coordination.