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Given the same inputs, execution is deterministic. SMP ordering differences are intentional and observable. No hidden timing dependencies exist.
Enforced by: per-cycle run loop with deterministic stage ordering, explicit barrier protocols, no undefined behavior in cross-CPU interactions (all coordination via atomic operations or mutex-protected paths).
Every architectural event is traceable: exceptions, interrupts, barriers, PAL transitions, reservation changes, MMIO accesses, IPI send/receive, TLB invalidations, and DMA operations. If it cannot be traced, it cannot be trusted.
Enforced by: EXECTRACE macros (ExecTrace.h) for PAL entry/exit, DEBUG_LOG in every subsystem with CPUId, IPIManager per-CPU statistics, MemoryBarrierCoordinator logging of initiation/acknowledgment/timeout, FaultDispatcher event queueing logs.
See Also: Section 3.18 – Instrumentation and Tracing; Section 9.12 – Debugging SMP Behavior.