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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 11 - Architectural Invariants > 11.8 Device and MMIO Invariants |
Devices operate asynchronously. CPU never blocks on device execution. Completion is interrupt-driven or polled.
Enforced by: IDeviceEmulator::onWrite() returns immediately (defers long operations to worker thread via QMetaObject::invokeMethod with Qt::QueuedConnection), device completion signals via IRQPendingState.
MMIO access is synchronous. Side effects occur immediately. MMIO is strongly ordered.
Enforced by: MMIOManager::handleRead()/handleWrite() dispatch directly to device handler function pointers (ReadFn/WriteFn) during EX stage. No buffering, no speculation, no deferral.
DMA operates on GuestMemory. DMA obeys access permissions. DMA completion does not imply ordering without barriers.
Enforced by: DMACoherencyManager handles cache flush/invalidate (TX: flush before device reads, RX: invalidate after device writes), breakReservationsOnCacheLine() on DMA writes, no implicit ordering from DMA completion to CPU instruction stream.
See Also: Chapter 10 – Devices and Memory-Mapped I/O (MMIO).