11.7 SMP Invariants

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11.7 SMP Invariants

11.7.1 True Symmetry

 

All CPUs are peers. No CPU has implicit authority. No global CPU lock exists.

 

Enforced by: ExecutionCoordinator creates identical CPUWorker instances, any CPU can be the boot processor (getAlphaBootProcessor()), all coordination is via explicit IPI/barrier protocols.

 

 

11.7.2 Per-CPU Independence

 

Each CPU has independent pipeline, registers, TLBs, write buffers, reservations, and PAL state. No CPU directly mutates another CPU's private state.

 

Enforced by: per-CPU AlphaPipeline, per-CPU register files, per-CPU FaultDispatcher via globalFaultDispatcher(cpuId), per-CPU CBox with WriteBufferManager, per-CPU reservation slot in global ReservationManager.

 

 

11.7.3 Shared Memory, Explicit Coordination

 

GuestMemory is shared. Visibility is not immediate. Coordination occurs only through barriers (MB → MemoryBarrierCoordinator → IPIs → acknowledgment), IPIs (IPIManager lock-free atomic slots), and PAL operations (implicit full serialization).

 

Enforced by: single global GuestMemory instance, WriteBufferManager defers stores per-CPU, MemoryBarrierCoordinator requires explicit IPI-driven acknowledgment from all active CPUs before barrier completes.

 

See Also: Chapter 9 - SMP Architecture.