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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 11 - Architectural Invariants > 11.6 Exception and Interrupt Invariants |
Faults are synchronous (detected in EX, associated with a specific instruction). Traps are synchronous but post-commit (delivered after instruction retirement). Interrupts are asynchronous (sampled between instructions). Each follows distinct delivery rules.
Enforced by: PendingEventKind (Exception/Interrupt/Ast/MachineCheck/Reset/PalCall), ExceptionClass_EV6 (32 values classifying fault type), IRQPendingState (asynchronous sampling).
Only one exception or interrupt is delivered at a time. Exceptions are prioritized deterministically (Reset > Machine Check > Arithmetic > ... > Interrupts). Interrupts are maskable and deferrable (by IPL). Faults affect only the current CPU.
Enforced by: FaultDispatcher delivers highest-priority event first (EventPriority enum), lower-priority events remain queued. Per-CPU FaultDispatcher instances ensure isolation. IRQPendingState::hasDeliverable(currentIPL) gates interrupt delivery.
All exceptions and interrupts enter PAL. No exception bypasses PAL. PAL is the sole authority for dispatch.
Enforced by: all exception delivery paths call enterPal() with appropriate PalEntryReason and PalVectorId_EV6 vector. All interrupt delivery calls PalService::deliverInterrupt(). No exception handler exists outside PAL code.