ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 2 - Execution Model

2.2.1 One Cycle per Iteration

EMulatR uses a cycle-based execution model:

•Each iteration of the AlphaCPU run loop represents one hardware clock cycle

•All architectural activity for that cycle is completed before the next iteration begins

•Timing, stalls, and ordering are expressed in cycles, not wall-clock time

This model provides:

•Deterministic execution — identical inputs always produce identical outputs

•Reproducible debugging — any execution trace can be replayed exactly

•Clear reasoning about stalls and serialization — all timing is expressed in discrete cycles

The cycle counter is maintained per-pipeline in AlphaPipeline::m_cycleCount and is incremented at the end of each tick() invocation.

2.2.2 Independent CPU Execution

In SMP configurations:

•Each CPU executes its own independent run loop

•Pipelines, registers, and TLBs are private per CPU

•Coordination occurs only through explicit shared mechanisms (GuestMemory, IPIs, barriers)

No CPU directly advances or inspects another CPU's pipeline. There is no shared CPU object and no master CPU. Each AlphaCPU is a peer that owns all of its own per-CPU state.

2.2 Cycle-Based Execution Model

2.2 Cycle-Based Execution Model

2.2.1 One Cycle per Iteration

2.2.2 Independent CPU Execution