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In multiprocessor configurations, the execution model does not assume lockstep execution between CPUs. Each CPU advances independently.

 

Shared effects between CPUs occur only through three explicit mechanisms:

•GuestMemory — the shared physical address space; LL/SC reservation invalidation on remote writes; the sole coherence authority

•Inter-processor interrupts (IPIs) — explicit signaling between CPUs; used for TLB shootdown, ASN-scoped invalidation, and cross-CPU coordination

•Barrier coordination — memory barriers enforce visibility ordering; write buffer draining ensures stores become globally visible

 

No CPU may directly access another CPU's pipeline, register files, TLBs, or write buffers. CPU identity (m_cpuId) is explicit and carried through all subsystems. The maximum CPU count is statically bounded at MAX_CPUS (64), while the active count is runtime-configured.

 

See Also: Chapter 9 - SMP Architecture; 9.4 Per-CPU vs Shared State; 9.7 Reservation Invalidation.