ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 2 - Execution Model

2.7.1 Execute Stage Semantics

All instruction semantics occur in the Execute (EX) stage:

•Integer arithmetic and logic (EBox)

•Floating-point operations (FBox)

•Memory access — loads and stores, address translation (MBox)

•Barrier setup and serialization requests (CBox)

•Privileged operations (PalBox)

•Branch condition evaluation (EBox)

Other pipeline stages perform bookkeeping only. The Fetch stage obtains instructions via IBox, the Decode stage validates grain association, and the Issue stage checks for hazards. None of these stages produce architecturally visible side effects.

In the implementation, stage_EX() within AlphaPipeline dispatches to the grain's execute() method, which in turn invokes the appropriate Box. Faults detected during EX (alignment, TLB miss, access violation) are recorded in the slot's fault state for delivery at WB.

2.7.2 Writeback as Commit Point

The Writeback (WB) stage is the sole architectural commit point:

•Registers are updated (note: register writes are physically performed in stage_MEM for forwarding, but become architecturally visible at WB)

•Memory stores become architecturally committed

•PC updates are finalized

•Instructions are considered retired

•Branch predictor is updated with actual outcomes

•Faults that reached retirement are dispatched

Any instruction that has not reached WB may be discarded without architectural side effects. This is the fundamental guarantee that enables precise exceptions, speculation recovery, and pipeline flushing.

Implementation Note: Register Write Timing

The pipeline processes stages from oldest to youngest (WB → MEM → EX → IS → DE → IF). Register writes physically occur in stage_MEM() so that stage_EX() in the same cycle can read the updated value — this is the forwarding path. Because stage_MEM() executes before stage_EX() in the same tick, a value written by an older instruction at MEM is immediately available to a younger instruction at EX.

// Execution order within tick():

// 1. stage_WB() - Retire, commit stores, dispatch faults

// 2. stage_MEM() - Register writeback (forwarding path)

// 3. stage_EX() - Read registers, execute instruction semantics

// 4. stage_IS() - Hazard check

// 5. stage_DE() - Decode (mostly NOOP — IBox already decoded)

// 6. stage_IF() - Instruction fetch

2.7 Execution and Commit Semantics

2.7 Execution and Commit Semantics

2.7.1 Execute Stage Semantics

2.7.2 Writeback as Commit Point

Implementation Note: Register Write Timing