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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 3 - Pipeline Architecture > 3.11 Backward Pipeline Advancement |
The pipeline advances from WB backward to IF each cycle. Within the tick() method, stages execute in this order:
stage_WB(); // Stage 5 — Retire, commit stores, dispatch faults (OLDEST)
stage_MEM(); // Stage 4 — Deferred register writeback (forwarding path)
stage_EX(); // Stage 3 — Read registers, execute instruction semantics
stage_IS(); // Stage 2 — Hazard check
stage_DE(); // Stage 1 — Decode / Box routing
stage_IF(); // Stage 0 — Instruction fetch (YOUNGEST)
This backward ordering provides three critical benefits:
•Prevents overwrite hazards — WB retires and frees a slot before younger stages attempt to fill it
•Enables result forwarding — MEM commits register writes before EX reads registers in the same cycle, so a value written by instruction N at MEM is immediately available to instruction N+2 at EX
•Supports precise exceptions — older instructions complete before younger ones, so flushing younger stages at any point produces a consistent architectural state
The pipeline uses a ring buffer of six physical PipelineSlot entries. The m_head index points to the oldest instruction (always in the WB logical position). Stage mapping uses modular arithmetic:
// Logical-to-physical mapping:
// stage(5) [WB ] = m_ringSlots[m_head] — Oldest
// stage(4) [MEM] = m_ringSlots[(m_head - 1 + 6) % 6]
// stage(3) [EX ] = m_ringSlots[(m_head - 2 + 6) % 6]
// stage(2) [IS ] = m_ringSlots[(m_head - 3 + 6) % 6]
// stage(1) [DE ] = m_ringSlots[(m_head - 4 + 6) % 6]
// stage(0) [IF ] = m_ringSlots[(m_head - 5 + 6) % 6] — Youngest
After all stages execute, advanceRing() increments m_head: m_head = (m_head + 1) % 6. This effectively retires the WB slot and makes a fresh slot available at the IF position.
See Also: 2.7.2 Execution and Commit Semantics (Writeback as Commit Point); cpuCoreLib/AlphaPipeline.h.