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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 3 - Pipeline Architecture > 3.9 Writeback Stage (WB) |
The Writeback stage is the sole architectural commit point. If an instruction reaches WB, it is guaranteed to be precise. If an instruction has not reached WB, its effects may be discarded without side effects.
stage_WB() executes the following steps in strict order:
1.Fault check — if slot.faultPending is true, discard pending commit, report FAULT action, invalidate slot, and return. The faulting instruction produces no architectural result.
2.CALL_PAL check — if the instruction is CALL_PAL, discard pending commit (pipeline is about to serialize), compute the PAL entry vector via computeCallPalEntry(), report PAL_CALL action, and return.
3.Store commit — if the instruction is a store (S_Store semantic), write data to GuestMemory via write64(slot.pa, slot.payLoad), then break LL/SC reservations on the affected cache line.
4.Branch predictor update — if branchTaken is set, update the CBox branch predictor with the actual outcome.
5.Retirement — call commitInstruction() which increments m_instructionsRetired, updates performance counters, and fires the EXECTRACE_WB_RETIRE trace macro.
6.Cleanup — invalidate the slot (slot.valid = false) and clear all state.
Registers are not written in WB. The physical register write occurs in stage_MEM() via commitPending() for forwarding purposes. WB handles store commits, fault dispatch, PAL entry, branch predictor updates, and instruction retirement. This separation is critical: register values must be available to EX in the same cycle, which requires the MEM-before-EX execution order.
// Store commit in WB:
if (slot.di.semantics & S_Store) {
MEM_STATUS memStat = m_guestMemory->write64(slot.pa, slot.payLoad);
m_reservationManager->breakReservationsOnCacheLine(slot.pa);
}
See Also: 3.14 Precise Exceptions; 3.11 Backward Pipeline Advancement; Chapter 7 - Exceptions, Faults, and Interrupts.