<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 3 - Pipeline Architecture > 3.8 Memory Stage (MEM)

Purpose

 

Despite its name, the MEM stage does not perform memory access. Memory access occurs in the EX stage via MBox. The MEM stage exists for:

•Deferred register commit — commitPending() executes at the top of MEM, writing the previous cycle's EX result to the register file. This provides the forwarding path: because MEM executes before EX in the same tick, a value written by an older instruction is immediately available to a younger instruction reading registers in EX.

•Stall propagation — if a memory barrier or write buffer drain is pending and not yet complete, the slot stalls

•Fault propagation — faults detected in EX are carried forward for delivery at WB

•Alignment with the architectural six-stage pipeline structure

 

What MEM Does Not Do

 

•No memory access — loads already completed in EX

•No cache lookup

•No store commit — stores commit in WB after all hazards are cleared

•No register writes — the deferred writeback from EX is committed via commitPending() at the top of MEM

 

Stall Conditions in MEM

 

if (slot.needsMemoryBarrier && !slot.memoryBarrierCompleted) {

 slot.stalled = true;

 return;

}

if (slot.needsWriteBufferDrain && !slot.writeBufferDrained) {

 slot.stalled = true;

 return;

}

 

See Also: 2.7.2 Execution and Commit Semantics(Writeback as Commit Point); 3.9 Writeback Stage (WB).