<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 3 - Pipeline Architecture > 3.14 Precise Exceptions

The pipeline guarantees precise exceptions. This means:

•All older instructions have committed — they have passed through WB and their architectural effects are visible

•No younger instruction has committed — they have not reached WB and their effects are discarded

•The faulting instruction is well-defined — its PC, fault type, and faulting address are recorded precisely

 

This property is fundamental to operating system correctness. The OS depends on being able to identify exactly which instruction faulted, resume or retry that instruction, and know that all prior instructions completed cleanly.

 

Exceptions are detected early (in EX) but delivered late (in WB). The fault is queued in the slot's faultPending/trapCode/faultVA fields, and the slot continues through the pipeline until it reaches WB. At WB, if faultPending is true, the slot triggers a FAULT action — the pipeline is flushed, the faulting PC is saved, and control transfers to the PAL exception handler.

 

See Also: Chapter 7 - Exceptions, Faults, and Interrupts; 3.9 Writeback Stage (WB).