3.15 LL/SC Interaction with Pipeline

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3.15 LL/SC Interaction with Pipeline

The pipeline enforces LL/SC (Load-Locked / Store-Conditional) semantics in coordination with the ReservationManager:

•LDL_L / LDQ_L (load-locked) — establishes a per-CPU reservation on the target cache line during EX

•STL_C / STQ_C (store-conditional) — tests the reservation in EX; succeeds only if the reservation is still valid; the store is committed atomically in WB

•Speculative execution may proceed between LDL_L and STL_C

 

Reservations are cleared on:

•Exception delivery

•Interrupt delivery

•Memory barriers

•PAL entry

•Remote store to the reserved cache line (SMP coherency via GuestMemory)

•Pipeline flush

 

No reservation survives a pipeline flush. Store commits in WB call breakReservationsOnCacheLine(slot.pa) to invalidate reservations held by other CPUs on the same physical address.

 

See Also: 5.11 Load-Locked / Store-Conditional (LL/SC); cpuCoreLib/ReservationManager.h.