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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 5 - Memory System Architecture > 5.11 Load-Locked / Store-Conditional (LL/SC) |
LL/SC uses reservations, not mutexes. This is an optimistic concurrency mechanism: the load-locked instruction establishes a reservation, and the store-conditional succeeds only if no other write has invalidated that reservation.
Properties:
•Reservation tracked per CPU — each CPU has exactly one reservation slot (CPUReservation struct with reservedCacheLine and hasReservation)
•Granularity is cache line — reservations are tracked at cache-line granularity (physical address masked to cache line boundary)
•Other CPUs may freely read/write — reservations are not locks
•Any write to the reserved cache line invalidates the reservation — via breakReservationsOnCacheLine()
The ReservationManager (ReservationManager.h, 153 lines) implements reservation tracking globally, not per-CPU. This ensures correct SMP invalidation and global visibility.
Key operations:
•setReservation(cpuId, physAddr) — called by LDL_L/LDQ_L in MBox during EX. Records the cache line for this CPU.
•checkReservation(cpuId, physAddr) — called by STL_C/STQ_C in MBox during EX. Returns true if the reservation is still valid for the same cache line.
•breakReservation(cpuId) — explicitly clears one CPU's reservation (called on exception, interrupt, PAL entry, pipeline flush)
•breakReservationsOnCacheLine(physAddr) — scans all active CPU reservations and clears any that match the given cache line. Called by WB stage after every store commit.
•breakAllReservations() — clears all CPU reservations (used at system reset)
Reservation clearing conditions: exception delivery, interrupt delivery, memory barriers, PAL entry, remote store to the reserved cache line, pipeline flush. No reservation survives a pipeline flush.
See Also: 3.15 LL/SC Interaction with the Pipeline; cpuCoreLib/ReservationManager.h.