ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 3 - Pipeline Architecture

Flush Causes

Pipeline slots may be flushed due to:

•Branch misprediction — actual outcome does not match prediction from IF

•Exception delivery — fault reached WB, younger slots must be discarded

•Interrupt delivery — asynchronous event requires pipeline drain

•CALL_PAL — pipeline serializes on PAL entry

•HW_REI — pipeline serializes on PAL exit

•Fatal fault — unrecoverable condition forces full pipeline invalidation

Only slots younger than the triggering instruction are flushed. On flush:

•All speculative slots are invalidated (slot.valid = false, slot.clear())

•WB state is preserved — the triggering instruction's architectural effects are maintained

•PC is reset to the correct target

•Fetch restarts cleanly from the corrected address

Flushes are precise and deterministic. No speculative side-effect survives a flush. No reservation survives a pipeline flush.