ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 2

EMulatR enforces a conservative but correct speculation model:

•Speculative execution may proceed past loads — loads complete synchronously in EX and do not block younger instructions

•Speculative execution must not proceed past barriers — MB, WMB, EXCB, TRAPB stall the frontend

•Speculative execution must not proceed past PAL entry — CALL_PAL serializes the pipeline

•Speculative state may always be discarded prior to WB — only the Writeback stage commits architectural state

This policy balances correctness with reasonable performance while maintaining debuggability. The emulator intentionally does not implement the speculative branch and memory access strategies of real EV6 silicon. Instead, speculation is limited to what the architecture requires for correctness, and any speculative slot may be safely flushed at any time before it reaches WB.

When a flush occurs (due to misprediction, fault, or PAL entry), younger stages (IF, DE, IS) are cleared by invalidating their slots:

for (int i = 0; i < STAGEEX; i++) {

stage(i).valid = false;

stage(i).clear();

}

2.6 Speculation Policy

2.6 Speculation Policy