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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 6 - Serialization and Stall Model |
This chapter defines how the AlphaCPU emulator enforces ordering, visibility, and completion in an otherwise weakly ordered execution model.
Alpha AXP does not guarantee memory ordering by default. Instead, ordering is established explicitly through serialization instructions. This chapter explains:
•Why serialization exists
•What is serialized (and what is not)
•How barriers interact with the pipeline
•How barriers stall and later release execution
•How this applies to SMP systems
This chapter is foundational to correctness in:
•SMP synchronization
•Atomic operations
•Device I/O
•Exception precision
•PAL mode transitions