ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 5 - Memory System Architecture

The EMulatR memory architecture mirrors Alpha AXP behavior while remaining debuggable, testable, and extensible.

GuestMemory — PA router and reservation tracker (286 lines)

SafeMemory — physical RAM with sparse backing (253 lines)

SparseMemoryBacking — on-demand page allocation (507 lines)

WriteBufferManager — per-CPU write buffering (218 lines)

ReservationManager — global LL/SC reservation tracking (153 lines)

Ev6Translator — VA→PA translation with page table walking (1,336 lines)

Total: 2,753 lines across six memory system headers.

1.GuestMemory is the single shared physical address space — one global instance, PA routing table, typed read/write API

2.SafeMemory is a dumb RAM backend — byte-addressable, bounds-checked, sparse-allocated, no ordering knowledge

3.Loads are synchronous; stores are deferred — two-phase store model (address in EX, commit in WB)

4.Ordering is never implicit — the weak memory model means no ordering without explicit barriers

5.Barriers enforce visibility and completion — MB, WMB, EXCB, TRAPB (full semantics in Chapter 6)

6.MMIO is strongly ordered — synchronous, unbuffered, no reordering

7.LL/SC uses optimistic reservations — per-CPU, cache-line granularity, globally tracked by ReservationManager

8.Translation is implementation-selected — page size and VA width chosen at bring-up, three-level page table with KSEG fast path

9.Memory faults are precise — detected in EX, delivered in WB, never speculative

10.Memory semantics are enforced by coordination, not timing

5.15 Summary