<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 5 - Memory System Architecture > 5.14 SMP Considerations

In EMulatR SMP systems:

•All CPUs share GuestMemory — one global instance, one backing store, one PA routing table

•Each CPU has independent write buffers — managed by per-CPU WriteBufferManager queues

•CBox coordinates global ordering — MB barriers propagate to the global MemoryBarrierCoordinator, which may send IPIs to other CPUs

•IPIs handle TLB shootdowns — when one CPU modifies page tables, other CPUs must invalidate their TLB entries

•Barriers may involve cross-CPU signaling — CBox::RequestMemoryBarrier() forwards to the ExecutionCoordinator for SMP-wide coordination

•LL/SC reservations are globally visible — breakReservationsOnCacheLine() scans all CPUs, not just the local one

 

The memory model remains weak unless explicitly serialized. Without barriers, CPUs may observe stores from other CPUs in any order. This is by design — it matches the Alpha AXP specification and ensures that only correctly synchronized software behaves correctly.

 

See Also: Chapter 9 - SMP Architecture; Chapter 6 - Serialization and Stall Model.