<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 5 - Memory System Architecture > 5.13 Interaction with Pipeline

The memory system interacts with the pipeline through well-defined contracts:

•Memory access occurs in the EX stage — MBox performs all loads and address computation for stores during grain->execute()

•MEM stage is a bookkeeping stage — commitPending() writes the deferred register result; barrier completion flags are checked

•WB commits architectural visibility — store data is written to GuestMemory; LL/SC reservations are invalidated on store commit

•Barriers stall fetch and advancement — CBox sets slot.stalled and slot.needsMemoryBarrier/needsWriteBufferDrain flags

•Exceptions flush the pipeline — memory faults trigger pipeline flush from WB

 

Memory does not advance the pipeline — it constrains it. The pipeline controls when instructions move forward; the memory system determines what happens when they execute and whether stalls are required.

 

See Also: Chapter 3 - Pipeline Architecture; 3.7 Execute Stage (EX).