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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 9 - SMP Architecture > 9.7 Memory Barrier Coordination |
MemoryBarrierCoordinator (MemoryBarrierCoordinator.h, 278 lines) is a singleton that manages global memory barrier synchronization across all CPUs. It is accessed via global_MemoryBarrierCoordinator().
Barrier state tracks: barrierInProgress (atomic bool), initiatingCpu, participatingCpus count, waitingCpus count (atomic), acknowledgedCpus count (atomic), and a QWaitCondition (barrierComplete) for blocking the initiating CPU until all acknowledgments arrive.
When CPU N executes MB in SMP, the following sequence occurs:
1.CBox::executeMB() drains the local write buffer
2.CBox::RequestMemoryBarrier() calls ExecutionCoordinator::requestMemoryBarrier(cpuId)
3.ExecutionCoordinator calls MemoryBarrierCoordinator::initiateGlobalMemoryBarrier(cpuId, activeCpuCount). If only one CPU is active, the barrier completes immediately (returns false). If a barrier is already in progress, the CPU joins the existing barrier (returns false).
4.The coordinator initializes barrier state and the initiating CPU self-acknowledges immediately
5.ExecutionCoordinator sends MEMORY_BARRIER_FULL IPIs to all other active CPUs via encodeIPIData(IPICommand::MEMORY_BARRIER_FULL, 0)
6.Initiating CPU calls waitForBarrierAcknowledge(cpuId) — blocks on QWaitCondition with a 2-second timeout
7.Target CPUs receive the IPI, enter PAL, drain their write buffers, and call acknowledgeMemoryBarrier(cpuId)
8.When all CPUs have acknowledged, the QWaitCondition is signaled, barrierInProgress is cleared, and the initiating CPU resumes
If the 2-second timeout expires before all CPUs acknowledge, the coordinator raises a machine check event (MachineCheckReason::SMP_BARRIER_TIMEOUT) via the FaultDispatcher. The MCES register's MME bit determines whether this is a fatal error or suppressed. This prevents a hung CPU from deadlocking the system.
WMB is local-only — drains the local write buffer, no global coordination, no IPIs. This makes WMB significantly cheaper than MB in SMP configurations. MB requires global coordination when activeCpuCount > 1. PAL barriers (MemoryBarrierKind::PAL) use the same global coordination path as MB.
See Also: memoryLib/MemoryBarrierCoordinator.h; emulatrLib/ExecutionCoordinator.h (requestMemoryBarrier).