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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 9 - SMP Architecture > 9.8 TLB Shootdown |
When a CPU modifies page tables, other CPUs may have stale TLB entries mapping the old translations. Without invalidation, memory safety would be violated — stale entries could allow access to freed pages, bypass permission changes, or map incorrect physical addresses.
1.Initiating CPU updates page table entries in GuestMemory
2.Initiating CPU sends TLB invalidation IPIs to other CPUs — IPICommand selects the invalidation scope: TLB_INVALIDATE_VA_ITB, TLB_INVALIDATE_VA_DTB, TLB_INVALIDATE_VA_BOTH, TLB_INVALIDATE_ASN, or TLB_INVALIDATE_ALL. For VA-specific invalidations, the VA is encoded in the IPI data via encodeIPIWithVA().
3.Target CPUs receive the IPI via checkInterrupts(), enter PAL, and call handleTLBShootdownIPI() which decodes the IPICommand and performs the appropriate TLB invalidation on the local ITB/DTB
4.Target CPUs acknowledge completion
5.Initiating CPU waits for acknowledgments, then resumes
Shootdowns are serialized operations — the initiating CPU stalls until all targets have acknowledged.
See Also: cpuCoreLib/AlphaCPU.h (handleTLBShootdownIPI).