<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 9 - SMP Architecture > 9.9 Reservation Invalidation in SMP

LL/SC reservation correctness in SMP depends on the ReservationManager's global scanning behavior. When any CPU commits a store in WB stage, CBox calls breakReservationsOnCacheLine(physAddr), which scans all active CPU reservation slots — not just the local CPU's. If any other CPU holds a reservation on the same cache line (64-byte aligned), that reservation is cleared.

 

Additional clearing conditions in SMP:

•Local store to same cache line — breaks own reservation

•Remote store to same cache line — breaks remote CPU's reservation via breakReservationsOnCacheLine()

•Barrier execution — MB may break reservations as part of write buffer draining

•PAL entry/exit — clears the local CPU's reservation only

•Exception/interrupt delivery — clears the local CPU's reservation only

•Pipeline flush — clears the local CPU's reservation

 

This ensures correctness without locking — LL/SC uses optimistic concurrency where the common case (no contention) succeeds with zero coordination overhead, and the contention case fails safely.

 

See Also: Section 5.11 – Load-Locked / Store-Conditional; cpuCoreLib/ReservationManager.h.