<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 9 - SMP Architecture > 9.10 PAL and SMP

PAL plays a central role in SMP correctness. It is the only execution context with the privilege level needed for cross-CPU coordination:

•Handles IPIs — IPI delivery enters PAL mode on the target CPU

•Performs TLB shootdowns — PAL code invalidates TLB entries and acknowledges

•Coordinates cache state — cache invalidation IPIs are processed in PAL

•Enforces privilege isolation per-CPU — each CPU's PAL boundary is independent

•Clears LL/SC reservations on transitions — PAL entry/exit always clears the local reservation

•Context switches — SWPCTX PAL call coordinates register save/restore, TLB management, and reservation clearing

 

PAL execution is always per-CPU. One CPU entering PAL mode does not affect any other CPU's execution state.

 

See Also: Chapter 8 – PAL and Privileged Boundary.