<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 9 - SMP Architecture > 9.11 Exception and Interrupt Isolation

In SMP, exceptions and interrupts are strictly isolated per-CPU:

•Exceptions affect only the faulting CPU — a DTB miss on CPU 0 does not stall or affect CPU 1

•Interrupts are delivered per-CPU — each CPU has its own IRQPendingState with independent pending levels and source masks

•FaultDispatcher is per-CPU — each CPU has its own event queue and pending flags

•Faults do not propagate across CPUs — no CPU can see another CPU's pending events

•System-wide effects occur only through explicit coordination — IPIs, global barriers, or shared GuestMemory writes

 

The one exception: machine checks triggered by SMP barrier timeouts (MachineCheckReason::SMP_BARRIER_TIMEOUT) are raised on the initiating CPU's FaultDispatcher but carry metadata about all participating CPUs (initiatingCpu, participatingCpus, acknowledgedCpus in PendingPropertyInfo).

 

See Also: Chapter 7 - Exceptions, Faults, and Interrupts; 7.10 Interrupt Handling.