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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 7 - Exceptions, Faults, and Interrupts > 7.10 Interrupt Handling |
Interrupt delivery depends on the current processor state. An interrupt is deliverable only when its IPL exceeds the current IPL (PS.IPL), interrupts are enabled, the CPU is not in the middle of a serialized barrier, and the CPU is not in a PAL entry sequence. Masked interrupts remain pending in the IRQPendingState until they become deliverable.
IRQPendingState (IRQPendingState.h, 378 lines) is the per-CPU interrupt tracking structure. It is designed for cross-thread safety: device threads may raise interrupts at any time, while the CPU thread checks for deliverable interrupts every cycle.
Key data structures:
•pendingLevelsMask (atomic<quint32>) — summary bitset: bit L set means at least one pending source at IPL L. Single fast check for "what needs attention".
•pendingSourcesByLevel (array of atomic<quint64>) — per-level source bitmask for up to 64 interrupt sources per level
•highestPendingLevel (atomic<quint8>) — cached highest pending IPL for ultra-fast per-instruction checking. 0xFF means "nothing pending." Updated atomically by raise/clear/claim.
•inServiceMask — CPU-thread-only mask tracking claimed (in-service) level-triggered interrupts
•Per-source static configuration — trigger mode (edge/level), SCB vector index, IPL assignment
AlphaCPU::checkInterrupts() is called each cycle. It reads the current IPL, tests hasDeliverable(currentIPL), claims the next interrupt via claimNext(), clears the SISR bit for software interrupts, and dispatches via PalService::deliverInterrupt(claimed). The interrupt handler saves PC and PS, selects the interrupt vector, and transfers control to the PAL interrupt handler.
IPIs are used for TLB shootdowns, cache invalidation, SMP coordination, and cross-CPU signaling. IPIs enter the system as interrupts and follow the same delivery rules. On receipt, handleTLBShootdownIPI() decodes the IPI command and performs the requested action (TLB invalidation by VA for ITB or DTB, TLB flush all, or global barrier acknowledgment).
Implementation: InterruptRouter.h (505 lines) handles interrupt routing and IPI dispatch.
See Also: coreLib/IRQPendingState.h; coreLib/InterruptRouter.h; cpuCoreLib/AlphaCPU.h (checkInterrupts, handleTLBShootdownIPI).