<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 7 - Exceptions, Faults, and Interrupts > 7.9 Exception Delivery and PAL Mode Entry

7.9.1 Delivery Conditions

 

An exception may be delivered when: no higher-priority event is pending, no barrier is blocking delivery, the pipeline is in a safe state, and the faulting instruction has reached WB stage.

 

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7.9.2 Architectural State Updates

 

On delivery, the pipeline calls AlphaCPU::enterPalMode() which performs the following state updates:

 

void enterPalMode(PalEntryReason reason, quint64 vector, quint64 faultPC) {

 // 1. Save complete context

 m_iprGlobalMaster->saveContext();

 

 // 2. Compute entry PC

 quint64 entryPC;

 if (reason == PalEntryReason::CALL_PAL_INSTRUCTION)

 entryPC = m_iprGlobalMaster->computeCallPalEntry(vector);

 else

 entryPC = vector;

 

 // 3. Set EXC_ADDR to faulting PC

 m_iprGlobalMaster->h->exc_addr = faultPC;

 

 // 4. Enter PAL mode: PC = vector | 0x1, IPL = 7, CM = KERNEL

 m_iprGlobalMaster->h->pc = entryPC | 0x1;

 m_iprGlobalMaster->h->setIPL_Unsynced(7);

 m_iprGlobalMaster->h->setCM(CM_KERNEL);

 

 // 5. Activate shadow registers for CALL_PAL

 if (reason == CALL_PAL_INSTRUCTION)

 m_iprGlobalMaster->setShadowEnabled(true);

 

 // 6. Flush pipeline

 m_alphaPipeline->flush("enterPalMode");

}

 

Key state changes: EXC_ADDR receives the faulting PC, EXC_SUM is updated for arithmetic exceptions, PS is updated (mode set to kernel, IPL raised to 7, interrupts masked), and the pipeline is flushed. The low bit of the entry PC (| 0x1) indicates PAL mode to the execution engine.

 

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7.9.3 PAL Entry Reasons

 

The PalEntryReason determines how the PAL vector is computed and what state is saved:

 

CALL_PAL_INSTRUCTION — explicit PAL call, vector computed from PAL_BASE + dispatch offset, shadow registers activated

TRAP — synchronous trap (arithmetic, software), vector from exception dispatch table

INTERRUPT — asynchronous interrupt, vector from interrupt dispatch table

FAULT — synchronous fault (translation, alignment, access violation), vector from exception dispatch table

 

See Also: cpuCoreLib/AlphaCPU.h (enterPalMode); Chapter 8 - PAL and Privileged Boundary.