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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 7 - Exceptions, Faults, and Interrupts > 7.8 Precise Exception Model |
When an exception is delivered, the following guarantees hold:
•All prior instructions have completed — every instruction older than the faulting instruction has retired through WB
•The faulting instruction is identified — EXC_ADDR holds the faulting PC
•No later instruction has executed — younger pipeline slots are invalidated
•Architectural state is consistent — register files, memory, and IPRs reflect only committed results
This is enforced by the detect-early/deliver-late model: faults are detected in EX stage (slot.faultPending, slot.trapCode, slot.faultVA), but not delivered until the faulting instruction reaches WB stage.
When delivering an exception from WB stage:
1.All younger pipeline slots are invalidated (slot.valid = false, slot.clear())
2.Write buffers are drained if required
3.LL/SC reservations are cleared via ReservationManager::breakReservation(cpuId)
4.Speculative state is discarded
5.EXC_ADDR is set to the faulting PC
6.Control transfers to PAL via enterPalMode()
See Also: 3.14 Precise Exceptions; 3.13 Flushing and Speculation.