ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 9 - SMP Architecture

9.4.1 Per-CPU State

The following state is strictly per-CPU. No other CPU may directly mutate this state:

•Pipeline slots (AlphaPipeline stages)

•Register files (integer R0–R31, FP F0–F31, shadow registers)

•Processor status (PS, CM, IPL, PAL mode flag)

•TLBs (ITB and DTB per-CPU instances)

•Write buffers (per-CPU WriteBufferManager queues, managed by CBox)

•LL/SC reservation slot (one CPUReservation per CPU in ReservationManager)

•FaultDispatcher (per-CPU pending events and flag bitmask)

•IRQPendingState (per-CPU interrupt tracking — device threads raise, CPU thread claims)

•CBox instance (per-CPU write buffer manager, barrier state machine)

The following state is shared across all CPUs:

•GuestMemory — single global instance (global_GuestMemory()), PA routing table, physical memory backing

•SafeMemory — one backing store, thread-safe via SparseMemoryBacking atomic page pointers

•MMIO regions — device state accessed by any CPU

•ReservationManager — global LL/SC tracking (breakReservationsOnCacheLine scans all CPUs)

•MemoryBarrierCoordinator — global barrier synchronization state

•IPIManager — cross-CPU message routing (atomic per-CPU IPI data slots)

•System-wide configuration (PAL_BASE, HWRPB, page size selection)

Shared state is accessed through controlled interfaces only — never via raw pointers or direct field access.