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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 9 - SMP Architecture > 9.5 Memory Visibility in SMP |
By default, stores may be buffered per-CPU (in WriteBufferManager), loads may observe stale values, and CPUs may see memory changes at different times. This behavior is architecturally correct — Alpha AXP's weak ordering model makes no guarantees about cross-CPU visibility without explicit barriers.
Visibility is enforced via MB (full memory barrier — drains local write buffer + global coordination), WMB (write barrier — drains local buffer only, no global coordination), EXCB/TRAPB (exception/trap precision), PAL transitions (implicit full serialization, global coordination for PAL-kind barriers), and certain device operations (MMIO writes bypass write buffer entirely).
When a barrier completes, prior stores become globally visible (committed to GuestMemory), prior loads are ordered appropriately, and other CPUs will observe changes on their next access.
Each CPU maintains its own logical write buffer via CBox → WriteBufferManager. There is no global write buffer. Stores retire from the pipeline before becoming globally visible. Buffers drain asynchronously, on barriers, and on PAL transitions. Buffers do not block other CPUs. ExecutionCoordinator::drainAllWriteBuffers() is available for system-wide operations (shutdown, halt).
See Also: 5.9 Write Buffers ; 6.7 MB - Full Memory Barrier; 6.8 WMB - Write Memory Barrier.