|
<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 5 - Memory System Architecture > 5.9 Write Buffers |
Write buffers exist to hide memory latency, improve pipeline throughput, and allow weak ordering. Each CPU has its own logical write buffer, managed by the WriteBufferManager (WriteBufferManager.h, 218 lines). CBox coordinates buffer management.
The WriteBufferManager provides per-CPU write queues with these operations:
•addEntry(cpuId, physAddr, data, size, timestamp, mmio) — enqueue a write
•drainCPU(cpuId, commitCallback) — flush all pending writes for a CPU, invoking the callback for each entry to commit it to GuestMemory
•getPendingWriteCount(cpuId) — query how many writes are buffered
•hasPendingWrites(cpuId) — quick check for any pending writes
•flushAllBuffers(commitCallback) — drain all CPUs (used at shutdown/halt)
Each WriteBufferEntry contains the physical address, data, size, timestamp, validity flag, and MMIO indicator.
Write buffers are drained on:
•MB — full memory barrier forces all pending writes to become globally visible
•WMB — write-only barrier forces store ordering
•EXCB — exception barrier ensures all pending exceptions and side-effects are resolved
•PAL entry — CALL_PAL serializes execution, draining write buffers before PAL code runs
•Before certain faults — ensure memory state is consistent before exception delivery
•Before shutdown or halt
Draining is coordinated by CBox via drainWriteBuffers(). If no WriteBufferManager is configured (m_writeBuffer == nullptr), CBox writes directly to GuestMemory (bypass mode).
See Also: 4.8 CBox - Cache / Coherency / Coordination Box; memoryLib/WriteBufferManager.h; coreLib/WriteBufferEntry.h.