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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 5 - Memory System Architecture > 5.8 Loads and Stores |
Loads execute synchronously in the EX stage. MBox performs address calculation, alignment checking, VA→PA translation via Ev6Translator, and then reads from GuestMemory. The data is placed immediately into slot.payLoad and marked for writeback (slot.needsWriteback = true). The register file update occurs via the deferred writeback path in MEM stage.
Loads do not stall by default, do not imply ordering, and do not serialize execution. They advance normally through the pipeline.
Stores follow a two-phase model:
1.EX stage — MBox computes the effective address, performs alignment checks and VA→PA translation, and places the address (slot.va, slot.pa) and data (slot.payLoad) into the pipeline slot. The store is not yet visible.
2.WB stage — the pipeline commits the store by calling m_guestMemory->write64(slot.pa, slot.payLoad), then breaks LL/SC reservations on the affected cache line via m_reservationManager->breakReservationsOnCacheLine(slot.pa).
Between EX and WB, the store data may enter a write buffer managed by CBox. Stores in the write buffer are not guaranteed to be visible to other CPUs, devices, or subsequent loads unless a barrier is used.
Stores may be reordered relative to other stores (in the write buffer) and relative to loads. This is the Alpha AXP weak ordering model. Only MB and WMB barriers enforce store visibility.
See Also: 5.9 Write Buffers; 5.10 Memory Barriers (preview); 4.7 MBox - Memory Box.