ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 17 – Address Translation, TLB, and PTE > 17.10 Architectural Invariants (Normative)

The following invariants govern the address translation subsystem. Violation of any invariant constitutes an emulator bug.

Layer Isolation: Layer 0 (SPAMShardManager) never walks page tables. Layer 1 (Ev6TLBInterface) provides only lookup/insert/invalidate operations. Layer 2 (PAL/MMU) is the exclusive location for page table walk logic.

Per-CPU Isolation: Each CPU's SPAM shard is fully independent. TLB lookup on CPU N never touches CPU M's shard. Only explicit shootdown IPIs or system-wide invalidation methods cross CPU boundaries.

Translation Locality: Data address translation occurs only in MBox during the EX stage. Instruction address translation occurs only in IBox during the IF stage. No other pipeline stage performs translation.

Shootdown Synchrony: TLB shootdown is always explicit and synchronized. The initiating CPU stalls until all target CPUs have acknowledged. No CPU may execute with a stale TLB entry after a shootdown completes.

Reservation Clearing: Any translation invalidation (TBIA, TBIAP, TBIS, or IPR-triggered invalidation) must clear LL/SC reservations. No STx_C may succeed against a mapping that has been invalidated.

Configuration Immutability: The VA option (page size, level bits, VA width) is selected once at configuration time and is immutable at runtime. TLB lookup uses the selected option exclusively — no per-lookup option scanning.

Canonical Enforcement: Non-canonical virtual addresses produce a translation fault. Canonicality is checked before TLB lookup.