<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 17 – Address Translation, TLB, and PTE

This chapter describes the implementation of address translation in EMulatR: how virtual addresses are converted to physical addresses, how TLB caches are organized and managed, how Page Table Entries (PTEs) are represented and manipulated, and how SMP coherence is maintained across per-CPU translation buffers. Where Chapter 5 defines the architectural contract for the memory system and Chapter 14 describes MBox as the execution domain that initiates translation, this chapter covers the concrete classes and data structures that implement the VA→PA path.

 

The translation subsystem is organized in three layers. Layer 0 (silicon) provides the raw TLB storage and lookup via SPAMShardManager and SPAMBucket — these know nothing about page tables or miss handling. Layer 1 (TLB interface) wraps Layer 0 with the Ev6SiliconTLB and Ev6TLBInterface classes, providing lookup, insert, and invalidate operations without trait or page-table knowledge. Layer 2 (PAL / MMU / miss handling) performs page table walks on TLB miss, raises translation faults (TNV, FOE, FOW, FOR), and calls Layer 1 insert to refill the TLB.

 

Scope: This chapter covers PTE representation (AlphaPTE, PTETraits, PTEView), TLB cache organization (SPAMShardManager, SPAMBucket), the Ev6SiliconTLB singleton, translation paths (ev6TranslateFastVA, ev6TranslateFullVA), replacement policies, TLB invalidation and SMP shootdown, ASN management, and the dual DTB architecture. It does not cover fault dispatch mechanics (Chapter 18) or interrupt delivery (Chapter 19).

 

See Also: Chapter 5 - Memory System Architecture (architectural contract, VA format); Chapter 14 – Execution Domains (“Boxes”) (MBox translation initiation); Chapter 15 – Memory System Implementation Details; Chapter 15 – Memory System Implementation Details (GuestMemory PA routing).