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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 17 – Address Translation, TLB, and PTE > 17.1 Alpha Virtual Address Format |
The Alpha AXP virtual address format is implementation-dependent, selected at CPU/board bring-up, not inferred from VA bits. The format is determined by two configuration inputs: pageShift (byte-within-page field width: 13, 14, 15, or 16 bits) and levelBits (Level2 and Level3 field widths: 10, 11, 12, or 13 bits). The implemented VA width (vaBits) varies by page size option.
All VA formats use the same three-level page table structure with a 2-bit segment field:
[Segment 2b] [L1 variable] [L2 levelBits] [L3 levelBits] [Offset pageShift]
Derived field boundaries:
offsetMask = (1ULL << pageShift) - 1
Segment = VA[vaBits-1 : vaBits-2] // 2 bits, always
L1 = VA[vaBits-3 : pageShift + 2*levelBits]
L1 width = vaBits - 2 - (pageShift + 2*levelBits)
L2 = VA[pageShift + 2*levelBits - 1 : pageShift + levelBits]
L3 = VA[pageShift + levelBits - 1 : pageShift]
Offset = VA[pageShift - 1 : 0]
Canonicality constraint: in a 64-bit VA register, bits above (vaBits-1) must be a sign-extension of bit (vaBits-1). Non-canonical addresses produce a translation fault.
Option |
Page Size |
pageShift |
levelBits |
vaBits |
L1 Width |
|---|---|---|---|---|---|
A |
8K |
13 |
10 |
43 (fixed) |
8 (fixed) |
B |
16K |
14 |
11 |
43–47 |
5–9 |
C |
32K |
15 |
12 |
43–51 |
2–10 |
D |
64K |
16 |
13 |
46–55 |
2–11 |
Note for Option D: the architecture states vaBits=44–55, but at vaBits=44 the L1 width is 0 bits, violating the minimum-2-bits-of-L1 constraint. In practice, vaBits must be ≥ 46 for 64K pages.
The VA option is selected once at configuration time via Ev6SiliconConfig, which sets basePageSize from the system configuration. The TLB lookup uses VPN = VA >> pageShift plus ASN, global flag, and mode checks. Do not scan VA options on every lookup — decode VA fields according to the selected option only. If mixed page sizes are later supported, page size becomes an attribute of the TLB entry (pageMask), not something inferred by reinterpreting VA field boundaries.
See Also: 5.4 Virtual Addressing and Translation; 5.4.4 Alpha VA Field Boundary Reference; Alpha AXP Architecture Reference Manual v6, Chapter 22.