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This section provides the normative bit-field boundary tables for all four Alpha AXP page size options. These are the decoding rules applied after the VA option is selected at CPU/board bring-up — they are not detectors. You cannot reliably distinguish 8K from 16K from 32K from 64K by examining a single VA; you must know the selected option.
Reference: Alpha AXP Architecture Reference Manual, Version 6 (1994), Memory Management chapter, "Virtual Address Format" (Figure 22-1, Table 22-2).
These values are configuration inputs selected by the implementation, not derived from VA bits:
pageShift — byte_within_page field width: 13, 14, 15, or 16 bits
levelBits — Level2 and Level3 field widths: 10, 11, 12, or 13 bits
vaBits — implemented VA width in bits (varies by page size; minimum 43)
offsetMask = (1ULL << pageShift) - 1
Segment = VA[vaBits-1 : vaBits-2] // 2 bits, always
L1 field = VA[vaBits-3 : pageShift + 2*levelBits]
L1 width = vaBits - 2 - (pageShift + 2*levelBits)
L2 field = VA[pageShift + 2*levelBits - 1 : pageShift + levelBits]
L3 field = VA[pageShift + levelBits - 1 : pageShift]
Offset = VA[pageShift - 1 : 0]
•VA space must be at least 43 bits
•At least 2 bits of Level1 must be implemented
•For reduced VA space, only a subset of low-order bits in Level1 are implemented
•Canonicality: in a 64-bit VA register, bits above (vaBits-1) must be a sign-extension of bit (vaBits-1)
pageShift=13, levelBits=10, vaBits=43 (fixed — only one width)
vaTop = 42
Segment = VA[42:41] 2 bits
L1 = VA[40:33] 8 bits
L2 = VA[32:23] 10 bits
L3 = VA[22:13] 10 bits
Offset = VA[12:0] 13 bits
Layout:
[42:41] [40:33] [32:23] [22:13] [12:0]
SEG L1 L2 L3 OFFSET(8K)
pageShift=14, levelBits=11, vaBits=43..47
vaTop = 42
Segment = VA[42:41] 2 bits
L1 = VA[40:36] 5 bits
L2 = VA[35:25] 11 bits
L3 = VA[24:14] 11 bits
Offset = VA[13:0] 14 bits
vaTop = 46
Segment = VA[46:45] 2 bits
L1 = VA[44:36] 9 bits
L2 = VA[35:25] 11 bits
L3 = VA[24:14] 11 bits
Offset = VA[13:0] 14 bits
Note: L2, L3, and Offset field positions are fixed regardless of vaBits. Only the Segment and L1 fields shift as vaBits increases.
Generic layout:
[vaTop:vaTop-1] [vaTop-2 : 36] [35:25] [24:14] [13:0]
SEG L1(5..9) L2(11) L3(11) OFFSET(16K)
pageShift=15, levelBits=12, vaBits=43..51
vaTop = 42
Segment = VA[42:41] 2 bits
L1 = VA[40:39] 2 bits (minimum allowed by ASA)
L2 = VA[38:27] 12 bits
L3 = VA[26:15] 12 bits
Offset = VA[14:0] 15 bits
vaTop = 50
Segment = VA[50:49] 2 bits
L1 = VA[48:39] 10 bits
L2 = VA[38:27] 12 bits
L3 = VA[26:15] 12 bits
Offset = VA[14:0] 15 bits
Generic layout:
[SEG] [L1 variable 2..10 bits] [L2 12] [L3 12] [OFFSET 15]
pageShift=16, levelBits=13, vaBits=46..55
Note: The ASA states vaBits=44..55, but at vaBits=44 the L1 width is 0 bits, which violates the minimum-2-bits-of-L1 constraint. In practice, vaBits must be ≥ 46 for 64K pages:
L1 width = vaBits - 2 - (16 + 2*13) = vaBits - 44
Minimum L1 ≥ 2 → vaBits ≥ 46
vaTop = 45
Segment = VA[45:44] 2 bits
L1 = VA[43:42] 2 bits
L2 = VA[41:29] 13 bits
L3 = VA[28:16] 13 bits
Offset = VA[15:0] 16 bits
vaTop = 54
Segment = VA[54:53] 2 bits
L1 = VA[52:42] 11 bits
L2 = VA[41:29] 13 bits
L3 = VA[28:16] 13 bits
Offset = VA[15:0] 16 bits
Generic layout:
[SEG] [L1 variable 2..11 bits] [L2 13] [L3 13] [OFFSET 16]
Do not scan VA options (8K/16K/32K/64K) on every lookup. Instead:
1.Select one option at CPU/board bring-up (configuration or CPU model default)
2.Decode VA fields according to that selected option
3.TLB lookup uses VPN = VA >> pageShift, plus ASN, global flag, and mode checks
4.If later emulating mixed page sizes, page size becomes an attribute of the TLB entry (pageMask), not something inferred by reinterpreting VA field boundaries
Option Page pageShift levelBits vaBits L1 width L2/L3 bits
------ ----- --------- --------- --------- ---------- ----------
A 8K 13 10 43 8 (fixed) 10 / 10
B 16K 14 11 43..47 5..9 11 / 11
C 32K 15 12 43..51 2..10 12 / 12
D 64K 16 13 46..55 2..11 13 / 13
See Also: 5.4.2 Virtual Addressing and Translation Responsibility; pteLib/ev6Translation_struct.h; Alpha AXP Architecture Reference Manual v6, Chapter 22.