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This chapter describes how memory is actually implemented inside EMulatR, not merely how it behaves architecturally. Where earlier chapters define what the memory system must guarantee, this chapter defines where data physically lives, how accesses are routed, how ordering is enforced, how SMP correctness is maintained, and how MMIO and devices are integrated.

 

The memory subsystem comprises approximately 4,600 lines of source across the memoryLib/ directory and supporting files in cpuCoreLib/ and coreLib/. The design follows a strict layered separation: GuestMemory is the physical address router and semantic authority; SafeMemory is the backing store; SparseMemoryBacking is the page allocator; and the WriteBufferManager, ReservationManager, and MemoryBarrierCoordinator enforce ordering and atomicity.

 

Scope: This chapter applies to GuestMemory, SafeMemory, SparseMemoryBacking, MMIO routing, write buffering, reservation tracking, and barrier coordination, but not to higher-level software policies or TLB translation (covered in Chapter 16).

 

See Also: Chapter 5 - Memory System Architecture (behavioral contract); Chapter 6 - Serialization and Stall Model; Chapter 10 – Devices and Memory-Mapped I/O (MMIO); Chapter 14 – Execution Domains (“Boxes”).