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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 14 – Execution Domains ("Boxes") |
The EMulatR processor model is organized into six discrete execution domains, each implemented as a self-contained C++ class known as a "Box." This architecture mirrors the physical partitioning of the Alpha 21264 (EV6) silicon, where independent functional blocks communicate through well-defined interfaces. Each box owns its own execution logic, scoreboard state, and fault reporting path, and interacts with other boxes only through explicit shared resources such as the PipelineSlot, GuestMemory, and the IPR state views.
All box classes are declared final (non-inheritable), constructed per-CPU via CPUIdType, and implemented as header-only compilation units with aggressive inlining (AXP_HOT, AXP_ALWAYS_INLINE, AXP_FLATTEN) for cycle-level performance.
Box |
Full Name |
Source Directory |
Primary Responsibility |
|---|---|---|---|
IBox |
Instruction Box |
IBoxLib/ |
Instruction fetch, decode, decode cache |
EBox |
Integer Execution Box |
EBoxLib/ |
Integer ALU, logic, shift, compare, conditional move |
FBox |
Floating-Point Box |
FBoxLib/ |
IEEE 754 arithmetic, FP conversion, FP conditional move |
MBox |
Memory Box |
MBoxLib_EV6/ |
Load/store execution, address translation, TLB, LDx_L/STx_C |
CBox |
Cache / Control Box |
CBoxLib/ |
Write buffer, memory barriers, branch prediction, control flow |
PalBox |
PAL Execution Box |
PalBoxLib/ |
CALL_PAL dispatch, HW_MFPR/HW_MTPR, PAL mode transitions |
See Also: Chapter 2.2 – Cycle-Base Execution Model; Chapter 12 – Pipeline Architecture (PipelineSlot); Chapter 15 – Memory Subsystem (GuestMemory, WriteBufferManager).