<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 14 – Execution Domains (“Boxes”) > 14.1 IBox – Instruction Box

The IBox is the instruction-supply front end of the emulated processor. It owns the fetch-decode pipeline and manages two levels of decode caching to accelerate repeated instruction sequences. On the Alpha 21264 silicon, the Ibox encompassed the fetch unit, branch predictor, instruction-stream TLB (ITB), issue queues, and register rename maps. In EmulatR, the IBox focuses specifically on fetch coordination and instruction decode; branch prediction and issue queuing are handled by the CBox and the pipeline manager respectively.

 

14.1.1 Responsibilities

 

•PC-driven instruction fetch coordination

•Instruction decode via the GrainResolver (opcode-to-grain mapping)

•Two-level decode cache: PcDecodeCache (virtual PC key, 64 entries) and PaDecodeCache (physical address key, 64 entries)

•FetchResult generation for downstream pipeline consumption

•VA-to-PA translation delegation to MBox for ITB lookups

•CALL_PAL detection and early routing to PalBox

 

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14.1.2 Key Interfaces

 

 

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14.1.3 Decode Cache Architecture

 

The IBox maintains two independent decode caches to avoid redundant instruction decoding. The PcDecodeCache is indexed by virtual PC and provides the fastest lookup path for tight loops and repeated code sequences. The PaDecodeCache is indexed by physical address and serves as a fallback when the virtual mapping has changed but the underlying physical instruction is still valid. A PA cache hit triggers automatic promotion into the PC cache for subsequent fast access.

 

Both caches use a direct-mapped structure with 64 entries and a simple index mask. Each entry stores the full DecodedInstruction along with the lookup key and a validity flag.

 

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14.1.4 Code Example – Fetch and Decode Path

 

AXP_HOT AXP_FLATTEN bool fetchAndDecode(FetchResult& fr) noexcept {

    const quint64 pc = m_iprGlobalMaster->h->pc;

    // Attempt cache-first lookup

    if (tryFetchFromCache(fr))

        return true;

    // Cache miss — full translate + memory fetch

    return fetchFromMemory(fr);

}

 

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14.1.5 Source Files

 

 

See Also: grainFactoryLib/DecodedInstruction.h – DecodedInstruction structure; coreLib/FetchResult.h – FetchResult pipeline transport type; pteLib/ev6Translation_struct.h – Translation result structure.