<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 13 – AlphaPipeline Implementation > 13.13 Summary

The AlphaPipeline is simple in structure, strict in correctness, and aggressively deterministic.

 

Implementation Inventory

 

AlphaPipeline.h — 2,088 lines (fully inline header, all stage implementations)

PipeLineSlot.h — 409 lines (slot structure, PendingCommit, control flags)

Total: 2,497 lines.

 

Key Takeaways

 

1.EX does everything — grain→execute() in stage_EX() is the only place instruction semantics occur

2.WB is the only architectural commit — store commits, retirement, fault dispatch, CALL_PAL detection

3.MEM writes registers — commitPending() in stage_MEM(), not stage_WB(). This is the key design decision.

4.RAW hazards resolved by execution order — WB→MEM→EX→IS→DE→IF reverse order means MEM writes before EX reads, same cycle, no forwarding needed

5.Ring buffer with 6 slots — m_head rotates, stage() maps logical to physical via modulo arithmetic

6.Barriers stall in MEM — needsMemoryBarrier/needsWriteBufferDrain flags checked in stage_MEM(), released by CBox

7.Flushes are precise — full flush clears all slots + MBox staging; partial flush preserves EX/MEM/WB

8.Exceptions detect-early/deliver-late — faultPending set in EX, dispatched in WB, younger instructions squashed

9.Store commits break reservations — breakReservationsOnCacheLine() on every store in WB

10.Speculation never leaks — stores only in WB, registers only via committed PendingCommit, no privilege leakage

 

See Also: Chapter 14 – Execution Domains ("Boxes") (next chapter).