<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 13 – AlphaPipeline Implementation > 13.12 LL/SC and Determinism

The pipeline enforces LL/SC semantics: speculation is allowed between LDL_L and STL_C, but reservations are cleared on exceptions, interrupts, barriers, PAL entry, and pipeline flush. STL_C retires atomically in stage_WB — the store-conditional check (reservation valid?) and the store commit happen in the same WB pass. No reservation survives a pipeline flush.

 

Store commits in stage_WB always call m_reservationManager→breakReservationsOnCacheLine(slot.pa), invalidating any reservation on the written cache line across all CPUs.

 

The pipeline guarantees determinism: in-order retirement (m_instructionsRetired increments monotonically), one architectural commit per cycle, no speculative side effects (stores only commit in WB, registers only write in MEM via committed pending), and no privilege leakage. All behavior is replayable and debuggable.

 

See Also: Section 5.11 – LL/SC; Section 11.4 – LL/SC Invariants.