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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 17 – Address Translation, TLB, and PTE > 17.11 Repository Directory Mapping |
The address translation subsystem spans the following directories:
Directory |
Key Files |
Responsibility |
|---|---|---|
pteLib/ |
alpha_pte_core.h, alpha_pte_traits.h, alpha_pte_traits_ev6_itb.h, alpha_pte_traits_ev6_dtb.h, alpha_pte_view.h, alpha_spam_manager.h, alpha_spam_bucket.h, TemplatePolicyBase.h, Ev6SiliconTLB_Singleton.h, DualDTBManagerInterface.h, ev6Translation_struct.h (~1,336 lines), calculateEffectiveAddress.h |
PTE representation, TLB cache (SPAM), translation engine, TLB singleton, replacement policies, EA calculation |
cpuCoreLib/ |
ReservationManager.h, AlphaCPU.h (handleTLBShootdownIPI) |
Reservation clearing on TLB invalidation, shootdown IPI handling |
coreLib/ |
IPI_core.h (TLB_INVALIDATE_* commands) |
IPI command definitions for shootdown protocol |
palLib_EV6/ |
PalService.h, PAL grains (TBIA, TBIAP, TBIS) |
PAL TLB invalidation dispatch, page table walk (Layer 2) |
configLib/ |
global_EmulatorSettings.h |
Page size / VA option configuration |
Total translation subsystem: The pteLib/ directory contains the bulk of the implementation, with ev6Translation_struct.h (~1,336 lines) being the largest single file. The SPAM cache infrastructure (manager, bucket, policies) adds approximately 1,500–2,000 lines. Supporting files in cpuCoreLib/, coreLib/, and palLib_EV6/ provide the shootdown, IPI, and PAL integration layers.
See Also: Chapter 14 – Execution Domains (“Boxes”) (MBox, IBox translation initiation); Chapter 15 – Memory System Implementation Details (GuestMemory PA routing after translation); Chapter 18 – Fault Dispatcher & Precise Exceptions (translation fault delivery).