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This chapter describes the implementation of the EMulatR exception and fault delivery subsystem: how exceptional events are created, classified, queued, prioritized, mapped to PAL vectors, and delivered while maintaining precise architectural state. Where Chapter 7 defines the architectural contract — faults are synchronous, interrupts are asynchronous, delivery is precise, PAL is the sole handler — this chapter describes the concrete classes, data structures, and pipeline interactions that enforce those guarantees.

 

The fault subsystem is organized around three core components. The FaultDispatcher (per-CPU, ~449 lines) is the central authority for event queueing, priority enforcement, and delivery timing. The PendingEvent structure (~420 lines) is the universal event carrier flowing from detection through delivery. The ExceptionMapping layer resolves ExceptionClass_EV6 classifications to PalVectorId_EV6 entries for PAL dispatch. Together with the ExceptionFactory (construction helpers) and the pipeline's detect-early/deliver-late model, these components implement Alpha AXP precise exception semantics.

 

Scope: This chapter covers FaultDispatcher internals, PendingEvent structure, ExceptionClass and PalVectorId mapping, ExceptionFactory event construction, pipeline fault detection and delivery flow, precise exception guarantees, and barrier interaction. It does not cover the IRQ system (Chapter 16), TLB miss handling (Chapter 17), or PAL mode internals (Chapter 20).

 

See Also: Chapter 7 - Exceptions, Faults, and Interrupts (architectural contract); 3.14 Precise Exceptions ; Chapter 8 - PAL and Privileged Boundary  (PAL mode entry).